Modern mobile devices, such as but not limited to cellular phones, personal data accessories and the like, include high-resolution full-color displays. These mobile devices are able to display high quality graphics, text, still images and video streams on their display panels. A video stream includes a sequence of images. For convenience of explanation graphics, test, and a still image are referred to as image. The image is represented by image data.
These mobile devices apply a multiple image data process operations in order to provide said high-quality images. Various image data processing operations include downsizing, over-sizing, color conversion, image rotation, alpha blending, de-blocking filtering, de-ringing filtering and the like.
Usually, a single mobile or stationary device can include more than a single image processor (also referred to as image data processor). An image processor is any component that can affect the value of image data by one or more prior art image processing stages. Some of these stages were mentioned above.
A double buffer includes a pair of buffers. Each of this pair of buffers can be accessed by a component, thus a double buffers can be accessed simultaneously by two components. If a video processing sequence is implemented by N processing components, a display controller that retrieves data from a last processing component and a first component that provides the image data to a first processing component then 2*(N+1) buffers or N+1 double buffers are required.
The following patents and patent applications, all being incorporated herein by reference, provide a brief overview of various buffering systems and methods applied for video processing: U.S. Pat. No. 6,765,622 of Rathnam et al., titled “Line-buffer reuse in vertical pixel-processing arrangement”; U.S. Pat. No. 6,128,026 of Brothers, III, titled “Double buffered graphics and video accelerator having a write blocking memory interface and method of doing the same”; and PCT patent application publication serial number WO 00/39804 of Quirk et al., titled “System for dual buffering input to dual port memory for a raster scanned display”.
Double buffers are usually implemented by DRAM memories. An image data processor reads information from a first buffer that belongs to a first page of the DRAM memory, processes the image data and then writes the processed image data to a second buffer that belongs to another page of the DRAM memory. During successive read and write operations the image data processor accesses one DRAM page (during the read operation) and then another DRAM page (during the write operation). This access pattern increases the access latency. This latency can affect the performance of the device, especially in devices that perform multiple access to the buffers.
There is a need to provide an efficient device and method for processing image data.